1. Field of the Invention
This invention relates in general to a method of fabricating memory cells and more particularly to a method of fabricating high density flat cells with buried bit lines by liquid phase deposition (LPD).
2. Description of Related Art
Memory ICs are widely used in an array of products that are becoming more and more light, thin, short, and small. This has increased the demand For memory ICs with high capacity, small surface area and high speed. In different sets of memory IC structures, memory cells with buried bit lines are widely used due to their smaller surface area and higher capacity. This is especially true For mask read-only memory (ROM), the most popular structure for mask ROMs.
To raise the density of high density flat cells with buried bit lines of a memory, the most effective way is to diminish the dimensions of each memory cell. However, to do so such problems as incomplete exposure of photoresist, and low memory cell punch-through voltage, still must be solved. To explain these problems in detail, partor the conventional process for fabricating mask read-oily memory (ROM) with buried bit lines is described below with reference to FIGS. 1a through 1c, which are schematic cross-sectional diagrams illustrating partof the conventional process of fabricating mask read-only memory with buried bit lines.
Referring to FIG. 1a, on a silicon substrate 11, such as a silicon substrate lightly doped with P-type impurities, a pad oxide layer 13 is formed as a protective layer for a later implantation process. A photoresist layer is coated over the pad oxide layer. The photoresist layer is exposed to light according to a predetermined pattern to change its solubility, and then part or photoresist material is removed in a developing process, whereby the photoresist layer 14 is completely formed while exposing areas for the source-drain electrodes.
Referring to FIG. 1b, when the implantation of impurities is performed, arsenic is generally adapted as an ion source because of its low diffusion coefficient, and N.sup.+ source-drain electrodes 20 with high density N-type impurities are formed.
Referring to FIG. 1c, the photoresist layer 14 is removed and then the pad oxide layer 13 is removed, whereby the conventional process of forming buried bit lines is completed. Other parts of the process of fabricating a mask ROM will not be further discussed.
The width 22 of source-drain electrodes 20, which is called "line width," is the same as that of the exposed area of photoresist layer 14. The channel width, which is called "slit" 24, is the same as that of the area covered by photoresist layer 14. According to the above-described conventional process, the ratio of line width 22 to slit 24 is limited in current state-of-the-art exposure machines. When the sum of the two widths is about 0.72 .mu.m, the following has been determined by experiment:
1. When the ratio of line width 22 to slit 24 is equal to or smaller than 0.565, the photoresist will not be exposed completely. PA1 2. When the ratio of line width 22 to slit 24 is equal to or larger than 1.17, the photoresist will be exposed completely.
There are two methods to reduce the dimension of the memory cell, which are as follows:
1. Reducing slit 24
Increasing the ratio of line width 22 to slit 24 results in better exposure of the photoresist. However, the punch-through voltage of the memory cell will be greatly reduced.
2. Reducing line width 22
Reducing the ratio of line width 22 to slit 24 results in the photoresist not being exposed completely by a current state-of-the-art exposure machine, which causes problems for the production of the source-drain electrodes 20.